Several data transfer devices for transferring data across an asynchronous boundary have been used in the past. These data transfer devices allow a single packet of data to be transferred from a first time domain across an asynchronous boundary to a second time domain at any one time.
A conventional data transfer device is shown generally in FIG. 1A by reference numeral 1. The conventional data transfer device 1 comprises a first transmitter/receiver combination, shown generally by reference numeral 2, which is used to transmit a single packet of data from the second time domain, on Side B of the asynchronous boundary 6, to the first time domain, on Side A of the asynchronous boundary 6 at any one time. The conventional device 1 also comprises a second transmitter/receiver combination, shown generally by reference numeral 4, which is used to transmit a single packet of data in the opposite direction from Side A to Side B. The transmitters/receivers 2 and 4 are identical, but each operates independently of the other. Each transmitter/receiver 2 and 4 also has separate request and acknowledge handshake signals, shown in FIG. 1A by the symbols REQ.sub.BA, ACK.sub.BA, REQ.sub.AB, ACK.sub.BA, which are used to transfer a single packet of data across the asynchronous boundary 6.
FIG. 1B shows a logic table 16 illustrating the transitions of signals on Side A and Side B during a data transfer from Side A to Side B. Steps 1 to 10 of FIG. 1B illustrate the transitions required to transfer a single packet of data A across the asynchronous boundary 6 from Side A to Side B. The packet of data A is initially stored in memory unit 8A of the second transmitter/receiver 4 and a request signal REQ.sub.AB is sent across the asynchronous boundary 6 from flip-flop 9A to synchronizer 12B on Side B. It generally takes two clock cycles on the receiver clock, in this case clock CLK.sub.B in Time Domain B, to receive the request signal REQ.sub.AB from flip-flop 9A. Once Side B receives the request signal REQ.sub.AB from Side A, Side B captures packet of data A by using or latching packet of data A.
Once packet of data A is captured, Side B asserts an acknowledge signal ACK.sub.BA through flip-flop 11B which is sent across the asynchronous boundary 6 to synchronizer 10A, as shown in steps 4 to 6 of FIG. 1B. It generally takes two clock cycles of the transmitter clock, in this case the clock CLK.sub.A in the first time domain, to receive the acknowledge signal ACK.sub.BA. The request signal REQ.sub.AB and the acknowledge signal ACK.sub.BA are then de-asserted as shown in steps 7 to 10 of FIG. 1B. A second packet of data B can then be stored in memory unit 8A of transmitter/receiver 4, as shown in step 11 of FIG. 1B, to be sent to Side B. Transmitter/receiver 2 has identical elements to transmitter/receiver 4 and if data is to be sent from Side B to Side A, transmitter/receiver 2 is used in a similar manner to transmitter/receiver 4.
It is apparent that the conventional device 1 requires several clock cycles on both clocks CLK.sub.A and CLK.sub.B to transfer a single packet of data A across the asynchronous boundary 6. Accordingly, a new packet of data cannot be sent across the asynchronous boundary 6 until the previous packet of data has been sent across the asynchronous boundary 6 and the handshake procedure has been completed. This is shown at least in FIG. 1B by the second packet of data B not being stored in the memory unit 8A until step 11, even though the second packet of data B may have arrived at the transmitter/receiver 4 much earlier. For example, if new packet of data B arrived at the transmitter/receiver 4 just after the request signal REQ.sub.AB for the previous packet of data A was asserted, the total latency for the new packet of data B would be equal to five signal transitions across the asynchronous boundary 6, namely REQ.sub.AB up, ACK.sub.BA up, REQ.sub.AB down, ACK.sub.BA down and REQ.sub.AB up again. It should also be noted that because these handshake signals do not emanate from the same side, the total latency will be limited by the slower of the two clocks CLK.sub.A and CLK.sub.B.
The conventional device 1 also suffers from the disadvantage that the throughput of data across the asynchronous boundary 6 is restricted to only one channel or transmitter/receiver 4. This is particularly limiting if one side, such as Side A, has a large amount of data, such as a burst of packets of data, to send to Side B. In this case, the burst will be limited by the transmission rate of the transmitter/receiver 4. Furthermore, the performance of several elements, such as a data bus on Side A, may be impaired while data is being sent across the asynchronous boundary 6 by the transmitter/receiver 4.
Also, the conventional device 1 is less reliable and prone to metastability failures because of the number of handshake signals REQ.sub.AB, REQ.sub.AB, ACK.sub.BA and ACK.sub.BA required and the number of gateways required to send and receive these handshake signals. A metastability failure results when data or a signal, such as the request signals REQ.sub.AB, REQ.sub.AB, or the acknowledge signals ACK.sub.AB, ACK.sub.BA, is received at the same time as the receiving clock signal, either CLK.sub.A or CLK.sub.B, is changing.
If this happens, the output from the gateway receiving the data or signal is unstable. The amount of time that the gateway is unstable is a decaying function which is a physical characteristic of the flip-flop gateway. This decreases the efficiency of the device, and, if the gateway stays unstable until the next cycle of receiving data, circuit failure could result. Therefore, there is a possibility of a metastability failure in the prior art devices each time one of the four handshake signals REQ.sub.AB, REQ.sub.BA, ACK.sub.B or ACK.sub.BA is received.